package brainfsck

import chisel3._
import chisel3.util._
import chisel3.simulator.ChiselSim

class SimulateTop extends Module {
    val io = IO(new Bundle {
        val outputPort = Decoupled(UInt(8.W))
    })

    private val outputBuffer = Module(new PassthroughBuffer(8))
    private val mem = Module(new DataMem(8))
    private val rom = Module(new SimulatedRom(8, "src/main/bf/hello.bf"))
    private val core = Module(new Brainfsck(8))

    core.io.memPort <> mem.io
    core.io.romPort <> rom.io
    core.io.outputPort <> outputBuffer.io.writePort
    core.io.inputPort.valid := false.B
    core.io.inputPort.bits := 0.U(8.W)
    outputBuffer.io.readPort <> io.outputPort
}

object Simulate extends App with ChiselSim {
    simulate (new SimulateTop) { dut =>
        dut.io.outputPort.ready.poke(true.B)
        for (i <- 0 until 65536) {
            if (dut.io.outputPort.valid.peekBoolean) {
                print(dut.io.outputPort.bits.peek.litValue.toChar)
            }
            dut.clock.step(1)
        }
    }
}
